The summary TMS320F2812 can usually realize that match with the time sequence of the daily peripheral chip, such as RAM, D/A,etc.; However, act as and meet reading, write cycle very slow input / output equipment, if when the liquid crystal reveals the module, printer, keyboard, need to design the corresponding outside hardware to wait for the circuit. This text carries on analysis and research to the outside interface time sequence of the fixed DSP chip; Canvass TMS320F2812 and liquid crystal emphatically to reveal the time sequence when the module is connected directly matches the question, and offer the relevant solution.
The key word TMS320F2812 slow speed has LMl9264A time sequence to control outside

Foreword
TMS320F2812 hereafter referred to as F2812 It is the instrument company of Dezhou of U.S.A. TI Company Product of new most generation in C2000 family put out. This chip adopts 32 operation, improve handling capacity greatly, can work in 150 MHz clock cycle can reach 6.67 ns frequently mainly ,Inside on it is advanced in its with outside if you can’t if you can’t set up by structure, last processor, use mainly for great to last apparatus management, high-performance control occasion. Compared with the other products of series C2000, operate flexibility, independence in time sequence of this chip. In order to further understand interface and designing technique of F2812 and slow peripheral hardware, it is necessary to discuss the characteristic that this chip time sequence is operated.

Reading and writing the time sequence characteristic of 1 F2812
In F2812, visits and realizes the reading, writing of external device by module XINTF of external interface. It is similar to the outside interface of C240X, but made the improvements of three respects too.
Original series TMS320LF240X, the memory space of procedure, space of data memory space and I/o map in the same address 0000 – FFFF ,The visit to them is distinguished by different orders; In F2812, the module of external interface has been divided into 5 pieces of fixed memory and videoed the area: XZCS0, XZCSl, XZCS2, XZCS6, XZCS7, can seek the space of memory outside one of the location 1 MB, has independent addresses.
There is a chip selection signal in each XINTF district of F2812. Among them, it have ground the chip selection signals of area until inside is “and ” Together, having made up a chip choice shared, for example XZCSo shares a chip selection signal XZCSO, ANDI with XZXSl, XZCS6 shares a chip selection signal XZCS6XZCS7 with XZCS7. In this way, the same external device can be connected to two districts, or can distinguish these two districts with decipher logic of outside.
5 can also count the wait state to video every district of the area separately to store fixedly, read and write and select communication the build-up time of number, activation time and keep time to carry on programming.

The gated time that programmable wait state, chip are chosen and can be programmed makes this interface independent from external memory and peripheral hardware to get in touch, can expand the outside flexibly and independently. Here, read, write to the external device the base clock visited is a clock xTIMCLK within xINTF. Through writing XTIMCLK location of XINTF-CNJF2 register, can dispose this clock into 1/2 equal to SYSCLK0UT and equal SYSCLKOUT, and shine upon in the intersection of XINTF and the intersection of outside and device of district going on, reading, writing, visiting, can divide to any piece into, set up, activate and follow 3 stages. Can set up the cycles of these three stages by corresponding XTIMINCO/1/2/6/7 register, make it meet demands of system. Reading and writing time sequence of F2812.

Can know by Figs. 1, 2, is setting up stage, the chip selection signal of the corresponding XINTF district turns into low level, the address is effective; Under the acquiescence situation, the cycle of this stage is a maximum – -Cycle of 6 XTIMCLKs. During the course of activating, visit to the external device: While reading and visiting, read and select the communication brass-wind instrument XRD Become low locking data DSP; While writing that visits, write that can enable signals XWE Become low and put the data on the data bus. Under the acquiescence situation, the cycle of this stage is a maximum – -14 XTIMCLKKs. During the course of following, read or write that selects communication number to become again for the high level, but their addresses still remain valid. Under the acquiescence situation, the cycle of this stage is a maximum – -Cycle of 6 XTIMCLKs.

Therefore can have, reading, writing cycle activate stage of F2812 Maximum 14 piece XTIMCLK cycle. If set up the frequency of XTIMCLK as 1/2 of SYSCLKOUT, read, write the maximum of cycle is 180 ns; And, it reads, writes the maintenance time of the operating data can reach cycle of 6 XTIMCLKs to the greatest extent – -80 ns. So, F2812 can realize that match with the time sequence of the daily peripheral chip, such as RAM, D/A,etc.; However, act as and meet reading, write cycle very slow input / output equipment, if when the liquid crystal reveals the module, printer, keyboard, need to design the corresponding outside hardware to wait for the circuit.

2 liquid crystals reveal reading and writing time sequence of module
Reveal the module as the example with LM19264A Chinese character figure liquid crystal that Shenzhen opens up the general little company, read and write time sequence.

The intersection of liquid crystal and module this make can cycle of E tcYc minimum signal 1500 ns, can make the intersection of signal and pulse width 700 ns in tWEH, twEL. When E is the high level, this liquid crystal module is in reading, writing cycle. If adopt the direct control method, CPU adopts the bus way to control the liquid crystal module, reading, writing the great number is risen to 146 times from 32 times the most cycle, thus can lengthen the wait state as about 4 μ S very conveniently of DSP, the actual effect has met the demands too.

5 DSP continuous to the liquid crystal module reads and writes visiting
When F2812 reveals the module carries on continuous reading, writing that is operated at the liquid crystal, two continuous ones read, write cycle activate stage During following stage and the setting-up stage of operation of time interval one piece at being operation, it is 12 XTIMCLK cycle 156 nss to be the biggest ,Can’t delay time. And can know by the chronological chart of the liquid crystal, the time interval of the continuous two times of operations to the liquid crystal, even can ask, it is 700 ns to be minimum when signal E level for being low. It is obvious, time sequence can’t be matched between the two. Then, add person’s time delay sentence between two orders continuously. Though the low efficiency that this kind of method realizes compared with the hardware, can well meet the designing requirement of the system.

6 conclusions
Independence, flexibility compared with existing DSP that the interface of outside of F2812 is designed. The method which it matches with the apparatus time sequence of the external slow speed that this text provides, it is easy to clear, it is direct to visit, control programming briefly, contribute to, understand the intersection of F2812 and the intersection of time sequence and characteristic of chip in depth, help to popularize chip this further.