Summary: Outside memory interface, I/O port introducing C8051F02X series one-chip computer which U.S.A. Cygnal Company produces dispose the method and question about paying attention to; Enumerate two disposition application about EMIF, I/O on this basis.

Keyword: C8051F02X EMIF I/O turn on or off alternately

U.S.A. Cygnal Company C8051F02X series one-chip computer integrates one grade of one-chip computers of mixed signal system on the chip together. This one-chip computer has 32/64 digits I/O port pin , 25MIPS in the intersection of system and programmable the intersection of Flash and memory, the intersection of 64KB and the intersection of outside and the intersection of memory and interface, 4352 of address in high-speed assembly line 8051 little the intersection of controller and kernel, 64KB ‘ 4096256 B characteristics such as RAM, each SPI, SMBUS/I2C and two UARTs serial interface independently,etc. in one. Its most outstanding advantage is, cross through setting up registers of switches control the digital resources in one to shine upon the outside I/O pin, this allows users to choose common I/O port and digital resource needed according to one’s own particular application. Certainly, set up figure cross register of switches, should consider the disposition issue of EMIF at first. It disposes difference, it is low or high to cause the one-chip computer to pass different ports I/O part that visited the memory outside slice and the memory videoed, and the figure cross switches distribute the external apparatus for P0.7 WR , P0.6 RD , P0.5 ALE Pin. If Fig. EMIF is set up as the many ways device mode.

1 EMIF and I/O dispose the method

1.1 Interface of the external memory EMIF Disposition

C8051F02X series MCU RAM with 4KB can be only shone upon slice, can shine upon 64KB outside data memory address space too, can also shine upon in one and outside one at the same time visit on the storing device space of a scene of memory within 4KB address, 4KB the above visited through EMIF Three ways. As to the last two kinds of memory work patterns, need to use MOVX, DPTR or MOVX and R0 R1 through the interface of the external memory I/O apparatus that the order visits the outside data memory and the memory videoes. But to 8 high addresses, must be by the external memory interface register EMI0CN Offer; And EMIF can be shone upon the low port P0- P3 the interface of the memory of the outside data series F020/2/3 Or high port P4- P7 series F020/2 ,And dispose it in order to reply by mode or not reply and use the mode etc.. Dispose it under the step of the interface of the external memory:

*Set up EMIF as the low port or high port;

*Set up EMIF in order to reply by mode or not reply and use the mode;

*Chosen the memory mode ‘ Way under slice, have piece choose, divide slices of way, take piece choose, divide slices of way, way outside the block ;

*Base while setting up the apparatus outside memory or one outside one;

*Choose the relevant I/O port register PnMOUT, P74OUT Output mode.

Interface of the external memory EMI Shine upon the low port P0- P3 Namely PRTSEL location EMIOCH.5 Put it for 0, such as PRTSEL position being 1, EMI shines upon the high port P4- P7 suitable for series P020/2 . If EMIFLE location XBR2.5 at this moment Set up as the logic 1, then, figures cross switches will not distribute the external apparatus for P0.7 WR , P0.6 RD , P0.5 ALE Pin If EMI sets up as to hit more modes ; If set as 0 in EMIFLE location, then the functions of P0.7, P0.6, P0.5 pin will be crossed switch registers or port latches will be determined. The interface of the external memory only carries out and uses the relevant port pin during MOVX order outside slice, once the intersection of MOVX and order finish, the intersection of port and latch or cross register of switches, resume control on pin of the port again.

1.2 I/O port disposed

Figure cross the intersection of switch and decoder according to use the intersection of priority and order of apparatus distribute the intersection of port and pin of P0- P7 to outside figure to set up. The distribution of the pin of the port is to begin from P0.0, the pin not used can be regarded as the generally common I/O pin, visit through reading and writing the corresponding port data register. Digital resources can enable the position 1 while crossing in figures in registers XBR0, XBR1, XBR2 of switches correspondingly, digital resources shine upon the port pin to I/O. For example: UART0EN location XBR0.2 Put it as 1, then, TX0 and RX0 pin shone upon to P0.0 and P0.1 respectively. Because UART0 have supreme priority, so when to can enable 1 position it, TX0 and the intersection of RX0 and pin always shine upon to P0.0 and P0.1. If the making of a digital peripheral hardware can not put 1 in the location, can’t be visited on I/O pin of its port. Figures cross after registers of switches are disposed correctly, through putting XBARE XBR2.4 1 in the location comes can turn on or off to make alternately. After switches can enable to cross. P0- P3 series F020/1/2/3 Or P0- P7 series F020/2 Exporting driving is forbidden automatically, thus avoided crossinging has written the fashionable conflict that produce on the pin of the port with register of switches and other registers. Attention: As to cross assigned input pin of switch ‘ For instance T0, INT0, RX0,etc. ,It output drives and is forbidden automatically, so, the values of data register of the port and PnMDOUT register have no effect on the states of these pins.

After giving to the corresponding I/O pin of digital resource allocation of the one-chip computer, should also set up it and output the way: Recommend and open a way with the drain-source resistance. Everybody of PnMDOUT register decides P0- P7 port pin output way, a certain position 1, this location outputs the way in order to recommend; Put 0, open a way for drain-source resistance and output the way. PnMDOUT register controls port pin output way, and switches have the pin of the port for the figure and have nothing to do with crossing. Attention: As to cross assigned input pin of switch ‘ For instance: SDA, SCL, RX0, RX1,etc. Dispose the way of opening a way for drain-source resistance automatically, and have no relations with the corresponding port disposes the arrangement of the register. But dispose to the general I/O pin in order that at the time of input, PnMDOUT correlated to this pin sets up and opens a way for drain-source resistance, port it disposes the intersection of register and location to be must 0 clear at the same time.

Though P4, P5, P6 and P7 do not have corresponding pin in C8051F021/3, the data register of the port still exists, and can be used by software. Because figure import thorough fare to keep active state, propose, in pin these ” unsettled ” The state, avoid causing unnecessary power consumption because of inputting and floating emptily for invalid logic level. Three kinds of following methods can prevent the occurrence of this kind of situation:

Pass WEAKPUD XBR2.7 Set up as, 0 come on, make, can pull part upward while being weak by logic;

Through writing P74OUT=0xFF, dispose the output ways of P4, P5, P6 and P7 as recommending the way;

Through writing 0 to the data register of the port, force the output states of P4, P5, P6 and P7 as the logic 0, namely P4 =0×00, P5 =0×00, P6 =0×00, P7 =0×00.

2 EMIF and I/O port disposes application

Following application accommodates C8051F020/2 one-chip computer too because of C8051F021/3 one-chip computer.

*Suppose, have, employ, need, dispose UART0, SMBus, UART1, INT0, INT1 ‘ 8 ,The work pattern of the memory is a way in slice; In addition, P1 port regarded as 4